The Facilities Mechanic A’s responsibility is to complete scheduled work and preventative maintenance tasks with written and verbal instructions to maintain and or repair the plant facilities as well as building and production equipment.
The IT Manager oversees the system and IT operational support team and is responsible for the network infrastructure server platforms, information security and network administration. Provides support to IT Director to establish and implement IT direction and planning, corporate systems and security policies, procedures, standards and budgeting requirements.
The Data Bus business unit within DDC is hiring a Digital Hardware/FPGA Engineer for the development of our next-generation data bus networking products. The engineer will perform a wide variety of tasks including the design, development, and verification testing of FPGAs. The engineer will also perform or support requirements specification, digital design, simulation, troubleshoot, hardware/software interface definition and systems integration testing. The engineer will work with cross-functional project teams, consisting of digital/analog hardware, software, and mechanical engineers in product definition/design/test/release to manufacturing, in support of the business unit.
The primary functions of the Engineering Assembly Technician is to build, repair, and maintain DDC's test/support equipment. The objectives of the position are to support the new product development efforts of the Engineering team, as well as to support the manufacturing efforts of the Production team.The position is essential to DDC’s success, with respect to both the development of new products, and to the shipment of existing products, in support of its primary revenue stream.
As a key member of DDC’s ASIC design team the Digital Design Engineer serves as an ASIC/SoC/FPGA lead architect for DDC’s next-generation of data bus networking products. This position plays a principal role in developing chip/board architecture, performing IP development/integration, and chip level RTL design & verification. This role is expected to hold responsibility for, and contribute positively to, all phases of ASIC/SoC/FPGA development, starting from creation of an architectural specification through ASIC/SoC/FPGA sign-off.